In recent electronic equipments including a cellular phone, a digital camera, etc., a severe demand is placed in speeding up an operation. In order to satisfy such a demand, it is required to use a so-called low-K material such as a porous silica for an interlayer insulating material of a semiconductor chip in order to reduce a parasitic capacitance generated between wiring patterns.
However, a low-K material is generally a mechanically brittle material, and tends to receive a damage due to a thermal strain generated during a joining process of a semiconductor chip. For example, a porous silica has a modulus of elasticity of 4 GPa to 8 GPa and, thereby, a mechanical strength of the porous silica is smaller than that of conventionally used interlayer insulating materials.
For this reason, a joining process to join a semiconductor chip using such a low-K material is performed at a low temperature in order to reduce a thermal strain generated in a substrate during the joining process. However, because a conventionally used lead-free solder requires a joining temperature of 217° C. or higher, it has been difficult to mount a semiconductor chip, in which a low-K material is used, on a printed wiring board.
In view of such a situation, Japanese Laid-Open Patent Application No. 2001-274201 suggests a technique to form a solder layer on a Cu wiring pattern on a printed wiring board, the solder layer having a lamination structure in which a tin (Sn) layer and a bismuth (Bi) layer are stacked sequentially. According to such a technique, it is considered that the solder layer fuses at a temperature of 139° C. according to an eutectic reaction of Sn and Bi, which enables joining a device such as a semiconductor chip or the like to connection electrodes at a low temperature.
Japanese Laid-Open Patent Application No. 2003-174252 also discloses a technique similar to the technique suggested in Japanese Laid-Open Patent application No. 2001-274201.
In the printed wiring board having an Sn layer directly formed on a Cu layer, Sn atoms in the Sn layer move into the Cu layer due to diffusion during a plated film producing process to form the Sn layer, which may cause a problem in that an intermetallic compound Cu6Sn5 is formed in a Cu electrode pad. As a result of formation of such an intermetallic compound, the Sn layer, which is formed on the Cu electrode pad, is consumed. Thus, even if a Bi layer is formed on the Cu electrode pad, the desired eutectic reaction cannot be produced.
In order to eliminate such a problem, according to the technique suggested in the above-mentioned patent document, it is required to set the film thickness of the Sn layer formed on the Cu layer large enough so that a depletion of Sn atoms does not occur and the Sn layer remains on the Cu electrode pad even if a large amount of Sn atoms are moved into the Cu electrode pad. However, according to such a structure, the film thickness of the Sn layer must be increased, which may cause a problem in that short-circuiting occurs between adjacent electrode pads through a thick solder layer when forming minute patterns with fine pitches.